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high voltage latch-up proof, dual spdt switches adg5436 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2011 analog devices, inc. all rights reserved. features latch-up proof 8 kv hbm esd rating low on resistance (<10 ) 9 v to 22 v dual-supply operation 9 v to 40 v single-supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v, and +36 v v ss to v dd analog signal range applications relay replacement automatic test equipment data acquisition instrumentation avionics audio and video switching communication systems functional block diagrams adg5436 s1a s1b in1 s2a s2b in2 d1 d2 switches shown for a logic 1 input. 09204-001 figure 1. tssop package adg5436 s2a d2 s2b s1a d1 s1b in2 en in1 logic 09204-002 switches shown for a logic 1 input. figure 2. lfcsp package general description the adg5436 is a monolithic cmos device containing two independently selectable single-pole/single-throw (spdt) switches. an en input on the lfcsp package enables or disables the device. when disabled, all channels switch off. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. both switches exhibit break-before-make switching action for use in multiplexer applications. the on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. product highlights 1. trench isolation guards against latch-up. a dielectric trench separates the p and n channel transistors thereby preventing latch-up even under severe overvoltage conditions. 2. low r on . 3. dual-supply operation. for applications where the analog signal is bipolar, the adg5436 can be operated from dual supplies up to 22 v. 4. single-supply operation. for applications where the analog signal is unipolar, the adg5436 can be operated from a single-rail power supply up to 40 v. 5. 3 v logic compatible digital inputs: v inh = 2.0 v, v inl = 0.8 v. 6. no v l logic power supply required.
adg5436 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual s upply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous cur rent per channel, sx or dx ............................. 7 absolute maximum ratings ............................................................8 esd caution ...................................................................................8 pin configurations and function descriptions ............................9 truth table for switches ..............................................................9 typical performance characteristics ........................................... 10 test circuits ..................................................................................... 14 terminology .................................................................................... 16 trench isolation .............................................................................. 17 applications information .............................................................. 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 6/ 11 rev. 0 to rev. a added i ss ?40c to +125c parameter .......................................... 5 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 19 7/ 10 rev ision 0: initial version
adg5436 rev. a | page 3 of 20 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10 %, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9.8 ? typ v s = 10 v, i s = ?10 ma; see figure 25 11 14 16 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ?r on 0.35 ? typ v s = 10 v , i s = ?10 ma 0.7 0.9 1.1 ? max on - resistance flatness, r flat (o n) 1.2 ? typ v s = 10 v, i s = ?10 ma 1.6 2 2.2 ? max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.05 na typ v s = 10 v, v d = ? 10 v; see fig ure 28 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.1 na typ v s = 10 v, v d = ? 10 v; see figure 28 0.4 2 12 na max channel on leakage, i d (on), i s (on) 0.1 na ty p v s = v d = 10 v; see figure 24 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gn d or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 170 ns typ r l = 300 ?, c l = 35 pf 235 285 316 ns max v s = 10 v; see figure 31 t on 173 ns typ r l = 300 ?, c l = 35 pf 230 280 351 ns max v s = 10 v; see figure 33 t off 124 ns typ r l = 300 ?, c l = 35 pf 160 193 218 ns max v s = 10 v; see figure 33 break - before - make time delay, t d 55 ns typ r l = 300 ?, c l = 35 pf 18 ns min v s1 = v s2 = 10 v; see figure 32 charge injection, q inj 200 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 34 off isolation ?78 db typ r l = 50 ?, c l = 5 pf, f = 1 m hz; see figure 27 channel - to - channel crosstalk ?58 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 26 total harmonic distortion + noise 0.009 % typ r l = 1 k?, 15 v p - p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 102 mhz typ r l = 50 ?, c l = 5 pf; see figure 30 insertion loss ?0.7 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 18 pf typ v s = 0 v, f = 1 mhz c d (off ) 62 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 83 pf typ v s = 0 v, f = 1 mhz
adg5436 rev. a | page 4 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9 /22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 9 ? typ v s = 15 v, i s = ?10 ma; see figure 25 10 13 15 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ?r on 0.35 ? typ v s = 15 v , i s = ?10 ma 0.7 0.9 1.1 ? max on - resistance flatness, r flat (on) 1.5 ? typ v s = 15 v, i s = ?10 ma 1.8 2.2 2.5 ? max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.05 na typ v s = 15 v, v d = ? 15 v; see figure 28 0.25 0.75 3.5 na max drain off leakage, i d (off ) 0.1 na typ v s = 15 v, v d = ? 15 v; see figure 28 0.4 2 12 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 15 v; see figure 24 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 158 ns typ r l = 300 ?, c l = 35 pf 217 260 293 ns max v s = 10 v; see figure 31 t on 164 ns typ r l = 300 ?, c l = 35 pf 213 256 287 ns max v s = 10 v; see figure 33 t off 110 ns typ r l = 300 ?, c l = 35 pf 1 52 173 194 ns max v s = 10 v; see figure 33 break - before - make time delay, t d 50 ns typ r l = 300 ?, c l = 35 pf 15 ns min v s1 = v s2 = 10 v; see figure 32 charge inj ection, q inj 250 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 34 off isolation ?78 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 channel - to - channel crosstalk ?58 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 26 total harmonic distortion + noise 0.007 % typ r l = 1 k?, 20 v p - p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 100 mhz typ r l = 50 ?, c l = 5 pf; see figure 30
adg5436 rev. a | page 5 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments insertion loss ?0.6 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 18 pf typ v s = 0 v, f = 1 mhz c d (off ) 63 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) 82 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 3. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 19 typ v s = 0 v to 10 v, i s = ?10 ma; see figure 25 22 27 31 max v dd = 10.8 v, v ss = 0 v on-resistance match between channels, ?r on 0.4 typ v s = 0 v to 10 v, i s = ?10 ma 0.8 1 1.2 max on-resistance flatness, r flat (on) 4.4 typ v s = 0 v to 10 v, i s = ?10 ma 5.5 6.5 7.5 max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off) 0.05 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 28 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.1 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 28 0.4 2 12 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/10 v; see figure 24 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 250 ns typ r l = 300 , c l = 35 pf 346 437 501 ns max v s = 8 v; see figure 31 t on 250 ns typ r l = 300 , c l = 35 pf 358 445 512 ns max v s = 8 v; see figure 33 t off 135 ns typ r l = 300 , c l = 35 pf 178 212 237 ns max v s = 8 v; see figure 33 break-before-make time delay, t d 125 ns typ r l = 300 , c l = 35 pf 50 ns min v s1 = v s2 = 8 v; see figure 32 charge injection, q inj 80 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 34
adg5436 rev. a | page 6 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments off isolation ?78 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 27 channel-to-channel crosstalk ?58 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 26 total harmonic distortion + noise 0.075 % typ r l = 1 k, 6 v p-p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 106 mhz typ r l = 50 , c l = 5 pf; see figure 30 insertion loss ?1.3 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 22 pf typ v s = 6 v, f = 1 mhz c d (off ) 67 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) 85 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 4. parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 10.6 typ v s = 0 v to 30 v, i s = ?10 ma; see figure 25 12 15 17 max v dd = 32.4 v, v ss = 0 v on-resistance match between channels, ?r on 0.35 typ v s = 0 v to 30 v, i s = ?10 ma 0.7 0.9 1.1 max on-resistance flatness, r flat(on) 2.7 typ v s = 0 v to 30 v, i s = ?10 ma 3.2 3.8 4.5 max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off) 0.05 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 28 0.25 0.75 3.5 na max drain off leakage, i d (off) 0.1 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 28 0.4 2 12 na max channel on leakage, i d (on), i s (on) 0.1 na typ v s = v d = 1 v/30 v; see figure 24 0.4 2 12 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 5 pf typ dynamic characteristics 1 transition time, t transition 174 ns typ r l = 300 , c l = 35 pf 246 270 303 ns max v s = 18 v; see figure 31 t on 180 ns typ r l = 300 , c l = 35 pf 247 270 301 ns max v s = 18 v; see figure 33
adg5436 rev. a | page 7 of 20 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments t off 127 ns typ r l = 300 ? , c l = 35 pf 179 193 215 ns max v s = 18 v; see figure 33 break - before - make time delay, t d 55 ns typ r l = 300 ? , c l = 35 pf 18 ns min v s1 = v s2 = 18 v; see figure 32 charge injection, q inj 250 pc typ v s = 18 v, r s = 0 ? , c l = 1 nf; see figure 34 off isolation ?78 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 27 channel - to - channel crosstalk ?58 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 26 total harmonic distortion + noise 0.03 % typ r l = 1 k ?, 18 v p - p, f = 20 hz to 20 khz; see figure 29 ?3 db bandwidth 98 mhz typ r l = 50 ? , c l = 5 pf; see figure 30 insertion loss ?0.8 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 30 c s (off ) 19 pf typ v s = 18 v, f = 1 mhz c d (off ) 40 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) 78 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9 /40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. continuous current per channel, s x or d x table 5 . parameter 25c 85c 125c unit continuous current, s x or d x v dd = + 1 5 v, v ss = ?1 5 v tssop ( ja = 1 12.6 c/w ) 122 77 44 ma maximum lfcsp ( ja = 30.4 c/w ) 217 116 53 ma maximum v dd = + 20 v, v ss = ?20 v tssop ( ja = 1 12.6 c/w ) 130 80 45 ma maximum lfcsp ( ja = 30.4 c/w ) 229 121 54 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 1 12.6 c/w ) 84 56 36 ma maximum lfcsp ( ja = 30.4 c/w ) 150 90 48 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 1 12.6 c/w ) 110 70 42 ma maximum lfcsp ( ja = 30.4 c/w ) 196 109 52 ma maximum
adg5436 rev. a | page 8 of 20 absolute maximum rat ings t a = 25c, unless o therwise noted. table 6. parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to + 48 v v ss to gnd +0.3 v to ? 48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx or dx pins 375 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current , sx or d x 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop (4- layer board) 112c/w 16- lead lfcsp 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c 1 overvoltages at the in x , sx, and dx pins are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution 2 see table 5 .
adg5436 rev. a | page 9 of 20 pin configurations and function descript ions in1 1 s1a 2 d1 3 s1b 4 nc 16 nc 15 nc 14 v dd 13 v ss 5 s2b 12 gnd 6 d2 11 nc 7 s2a 10 nc 8 in2 9 nc = no connect adg5436 top view (not to scale) 09204-003 figure 3. tssop pin configuration notes 1. exposed pad tied to substrate, v ss . 2. nc = no connect. pin 1 indicator 1 d1 2 s1b 3v ss 4 gnd 11 v dd 12 en 10 s2b 9 d2 5 nc 6 in2 7 nc 8 s2a 15 in1 16 s1a 14 nc 13 nc top view (not to scale) adg5436 09204-004 figure 4 . lfcsp pin configuration table 7 . pin function descriptions pin no. tssop lfcsp nemonic function 1 15 in1 logic control input 1. 2 16 s1a source terminal 1a . this pin c an be an input or output. 3 1 d1 drain terminal 1 . this pin c an be an input or output. 4 2 s1b source terminal 1b . this pin c an be an input or output. 5 3 v ss most negative power supply potential. 6 4 gnd groun d (0 v) reference. 7, 8, 14 to 16 5, 7, 13, 14 nc no connect. 9 6 in2 logic control input 2. 10 8 s2a source terminal 2a . this pin c an be an input or output. 11 9 d2 drain terminal 2 . this pin c an be an input or output. 12 10 s2b source terminal 2b . t his pin c an be an input or output. 13 11 v dd most positive power supply potential. n/a 12 en active high digital input. when this pin is low, the device is disabled and all switches are off. when this pin is high, inx logic inputs determine the on switc hes. ep exposed pad the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substr ate, v ss . truth table for swit ches table 8 . adg5436 tssop truth table in sa sb 0 off on 1 on off table 9 . adg5436 lfcsp truth table n in sa sb 0 x off off 1 0 off on 1 1 on off
adg5436 rev. a | page 10 of 20 typical performance characteristics 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 10 ?5 0 5 10 15 20 on resis t ance () v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +10v v ss = ?10v v dd = +13.5v v ss = ?13.5v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +11v v ss = ?11v 09204-134 figure 5 . on resistance vs. v s , v d ( dual supply ) 0 2 4 6 8 10 12 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resis t ance () v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09204-135 figure 6. on resistance vs. v s , v d ( dual supply ) included 0 5 10 15 20 25 0 2 4 6 8 10 12 14 on resis t ance () v s , v d (v) t a = 25c v dd = +9v v ss = 0v v dd = +10v v ss = 0v v dd = 10.8v v ss = 0v v dd = 11v v ss = 0v v dd = 13.2v v ss = 0v v dd = 12v v ss = 0v 09204-041 figure 7. on resistance vs. v s , v d (single supply ) 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 40 45 on resis t ance () t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v v s , v d (v) 09204-042 figure 8. on resistance vs. v s , v d (single supply ) 0 2 4 6 8 10 12 14 18 16 ?15 ?10 ?5 0 5 10 15 on resis t ance () v s , v d (v) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = +15v v ss = ?15v 09204-140 figure 9 . on resistance vs. v d or v s for different temperatures, 15 v dual supply 0 2 4 6 8 10 12 14 16 ?20 ?15 ?10 ?5 0 5 10 15 20 on resis t ance () v s , v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09204-141 figure 10 . on resistance vs. v d or v s for different temperatures, 20 v du al supply
adg5436 rev. a | page 11 of 20 0 5 10 15 20 25 30 024681012 on resistance ( ? ) t a = +125c t a = +85c t a = +25c t a = ?40c v dd = 12v v ss = 0v v s , v d (v) 09204-142 figure 11. on resistance vs. v d or v s for different temperatures, 12 v single supply 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 40 on resistance ( ? ) v s , v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09204-143 figure 12. on resistance vs. v s (v d ) for different temperatures, 36 v single supply 0 255075100125 leakage current (na) temperature (c) 0.6 ?0.2 0.4 ?0.6 0 ?0.4 0.2 v dd = +15v v ss = ?15v v bias = +10v/?10v i d , i s (on) + + i d , i s (on) ? ? i s (off) ? + i d (off) ? + i s (off) + ? i d (off) + ? 09204-047 figure 13. leakage currents vs. temperature, 15 v dual supply 0.8 ?0.2 0.6 0.4 ?0.6 0 ?0.4 0.2 0 255075100125 leakage current (na) temperature (c) v dd = +20v v ss = ?20v v bias = +15v/?15v i d , i s (on) + + i d (off) + ? i s (off) + ? i d (off) ? + 09204-048 i s (off) ? + i d , i s (on) ? ? figure 14. leakage currents vs. temperature, 20 v single supply 0 25 50 75 100 125 leakage current (na) 0.6 0 0.4 ?0.2 0.2 i d , i s (on) ? ? i d (off) + ? i s (off) ? + i d , i s (on) + + i s (off) + ? temperature (c) 09204-046 i d (off) ? + v dd = 12v v ss = 0v v bias = 1v/10v figure 15. leakage currents vs. temperature, 12 v single supply 0 25 50 75 100 125 leakage current (na) temperature (c) 0.6 0.8 ?0.2 0.4 ?0.6 0 ?0.4 0.2 i d , i s (on) + + i d (off) + ? v dd = 36v v ss = 0v v bias = 1v/30v i d (off) ? + i s (off) + ? i s (off) ? + i d , i s (on) ? ? 09204-049 figure 16. leakage currents vs. temperature, 36 v single supply
adg5436 rev. a | page 12 of 20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 off isol a tion (db) frequenc y (hz) 10k 100k 1m 10m 100m 1g 1k t a = 25c v dd = +15v v ss = ?15v 09204-044 figure 17 . off isolation vs. frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 cross t alk (db) frequenc y (hz) 10k 100k 1m 10m 100m 1g t a = 25c v dd = +15v v ss = ?15v 09204-040 figure 18 . crosstalk vs. frequency 0 50 100 150 200 250 300 350 400 450 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09204-034 figure 19 . charge injection vs. source voltage no decoupling capacitors ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 acpsrr (db) frequenc y (hz) 1k 10k 1m 10m 100k t a = 25c v dd = +15v v ss = ?15v decoupling capacitors 09204-038 figure 20 . acpsrr vs. frequency 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 5k 10k 15k 20k thd + n (%) frequenc y (hz) load = 1k t a = 25c v dd = 12v, v ss = 0v, v s = 6v p-p v dd = 15v, v ss = 15v, v s = 15v p-p v dd = 20v, v ss = 20v, v s = 20v p-p v dd = 36v, v ss = 0v, v s = 18v p-p 09204-039 figure 21 . th d + n vs. frequency ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 insertion loss (db) frequenc y (hz) 10k 100k 1m 10m 100m 1k 1g t a = 25c v dd = +15v v ss = ?15v 09204-037 figure 22 . bandwidth
adg5436 rev. a | page 13 of 20 0 50 100 150 200 250 300 350 400 ?40 ?20 0 20 40 60 80 100 120 time (ns) tempera ture (c) v dd = 12v v ss = 0v v dd = 36v v ss = 0v v dd = +15v v ss = ?15v v dd = +20v v ss = ?20v 09204-035 figure 23 . t transition time vs. temperature
adg5436 rev. a | page 14 of 20 test circuits sxa/sxb dx a v d i d (on) nc nc = no connect 09204-025 figure 24. on leakage i ds sxa/sxb dx v s v 09204-023 figure 25. on resistance channel-to-channel crosstalk = 20 log v out gnd sxa dx sxb v out network analyzer r l 50 ? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss inx 09204-032 figure 26. channel-to-channel crosstalk v out 50? network analyzer r l 50? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb off isolation = 20 log v out v s 09204-030 figure 27. off isolation sxa/sxb dx v s a a v d i s (off) i d (off) 09204-024 figure 28. off leakage v out r s audio precision r l 1k? inx v in sxa/sxb dx v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 09204-033 figure 29. thd + noise v out 50? network analyzer r l 50 ? inx v in sxa d x v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sxb insertion loss = 20 log v out with switch v out without switch 09204-031 figure 30. bandwidth
adg5436 rev. a | page 15 of 20 inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300 ? 50% 50% 90% 50% 50% 90% t on t off v in v out v in 09204-026 figure 31. switching times inx v out dx sxa v dd v ss v dd v ss gnd c l 35pf sxb v in v s 0.1f 0.1f r l 300? 80% t d t d v out v in 09204-027 figure 32. break-before-make time delay t d output inx 50? 300 ? gnd sxa sxb dx 35pf v in en v dd v ss v dd v ss v s 3v 0v output 50% 50% t off (en) t on (en) 0.9v out 0.9v out enable drive (v in ) 09204-028 figure 33. enable delay, t on (en), t off (en) v in (normally closed switch) v out v in (normally open switch) off ? v out on q inj = c l ? v out inx v out dx sxa v dd v ss v dd v ss gnd c l 1nf nc sxb v in v s 0.1f 0.1f 09204-029 figure 34. charge injection
adg5436 rev. a | page 16 of 20 terminology i dd i dd represents t he positive suppl y current. i ss i ss represents t he negative supply current. v d , v s v d and v s represent t he analog voltage on terminal d and terminal s , respectively . r on r on represents t he ohmic resistance between terminal d and terminal s. ?r on ?r on represents the difference between the r on of any two channels . r flat (on) f latness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is t he source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s (on) represent t he channel leakage current s with the switch on. v inl v inl is the maximum input voltag e for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent t he low and high input current s of the digital input s. c d (off) c d (off) represents t he off switch drain capacitance, which is measured with referenc e to ground. c s (off) c s (off) represents t he off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitance s , which are measured with reference to ground. c in c in is t he digital input capacitance. t on t on represents the delay between applying the digital control input and the output switching on . t off t off represents t he delay between applying the digital control input and the output switching off. t d t d represents the o ff time measured between the 80% point of both switches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off switch. charge injection charge injection is a measure o f the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth b andwi dth is the frequency at which the output is attenuated by 3 db. on response on response is t he frequency response of the on switch. insertion loss insertion loss is the loss due to the on resistance of the switch. total harmonic distortion + noise (th d + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by thd + n . ac power supply rejection ratio (acpsrr) acpsrr is t he ratio of the amplitude of signal on the output to the amplitude of the modulation. th is is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p.
adg5436 rev. a | page 17 of 20 trench isolation in the adg 5436, an insulating oxide layer (trench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch -u p proof switch. in junction isolation, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltage conditions, this diode can become forward - biased. a silicon controlled rectifi er (scr) type circuit is formed by the two transistors causing a significant amplification of the current that , in turn, leads to latch - up. with trench isolation, this diode is removed, and the result is a latch - up proof switch. 09204-045 nmos pmos p-well n-well buried oxide layer handle wafer trench figure 35 . trench isolation
adg5436 rev. a | page 18 of 20 applications informa tion the adg54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace and other harsh environments that are prone to latch - up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. the adg5436 high voltage switches allow single -supply operation from 9 v to 40 v and dual supply operation from 9 v to 22 v. the adg5436 (as well as other select devices within th is family ) achieve s an 8 kv human body model esd rating , which provides a robust solution eliminating the need for separate protect circuitry designs in some applications.
adg5436 rev. a | page 19 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 36 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant to jedec standards mo-220-wggc. 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad pin 1 indicator 4.10 4.00 sq 3.90 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 08-16-2010-c figure 37 . 16 - lead lead frame chip scale package [lfcsp_w q] 4 mm 4 mm body, very very thin quad (cp - 16 -17) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5436 bruz ?40c to +125c 16- lead thin shrink small outline package [tssop] ru -16 adg 5436 bruz - reel7 ?40c to +125c 16- lead thin shrink small outline pack age [tssop] ru -16 adg 5436 bcpz - reel 7 ?40c to +125c 16- lead lead frame chip scale package [lfcsp_ w q] cp -16 -17 1 z = rohs compliant part.
adg5436 rev. a | page 20 of 20 notes ? 2010 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09204 -0- 6/11(a)

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